1. Technical Field
The present invention relates to a package and a packaging method, and more particularly, to a stack package in which external leads are connected to one another so as to stack a plurality of packages, and a stack packaging method for forming the stack package.
2. Description of the Related Art
Over the past several years, semiconductor manufacturers have endeavored to increase the degree of integration of a semiconductor device and to reduce the size of the semiconductor device. To accomplish this, many research developments and facility investments must be made in order to increase the degree of integration in a semiconductor wafer manufacturing process and hence, significant costs are required. As an example, in the case of a semiconductor memory device, in order to increase the degree of integration from 64 MB DRAM to 256 MB DRAM, many technical problems must be solved in the semiconductor wafer manufacturing process and new equipment must be purchased.
However, a method for increasing the degree of integration without the costs associated with technical developments and facility investments has been developed in a semiconductor package manufacturing process that is subsequent to the semiconductor wafer manufacturing process. The method is to assemble a plurality of semiconductor chips in one semiconductor package. This is because, in a technique for manufacturing a semiconductor package by mounting a plurality of semiconductor chips in one semiconductor package, the degree of integration can be increased with less effort than that required for increasing the degree of integration in a wafer state. For example, if four semiconductor chips of 64 MB DRAM each are inserted and assembled in one semiconductor package, a 256 MB DRAM can be easily manufactured.
Initially, a plurality of semiconductor chips were arranged in a horizontal direction and were assembled in one semiconductor package. However, demands for reducing the size of a semiconductor package was not satisfied by this approach. Thus, most multi-chip semiconductor packages are now manufactured in such a way that a plurality of semiconductor chips are arranged vertically in a semiconductor package.
FIG. 1 is a perspective view of a conventional stack package. Referring to FIG. 1, two packages including an upper package 20 and a lower package 10 are stacked vertically, and external leads of each of the upper package 20 and the lower package 10 are soldered so as to be electrically connected to one another. When a stack package operates as memory, any one of the semiconductor chips (not shown) built in the upper package 20 and the lower package 10, respectively, must be selectively accessed when data is input and output. A Chip Select signal for selecting any one of the semiconductor chips built in the upper package 20 and the lower package 10, respectively, is input through a Chip Select (hereinafter, referred to as /CE) pin.
When a /CE pin 24 of the upper package 20 and a /CE pin 14 of the lower package 10 are arranged in the same sequence, as illustrated in FIG. 1, if a Chip Select signal is selectively input to a semiconductor chip, the /CE pin 24 of the upper package 20 and the /CE pin 14 of the lower package 10 should be electrically isolated from each other. To this end, the /CE pin 24 among the external leads of the upper package 20 is cut so as not to contact the /CE pin 14 of the lower package 10. However, in some cases, solder drops on the /CE pin 14 of the lower package 10 from the cut /CE pin 24 so that the two /CE pins 14 and 24 may be shorted together. In addition, when the cutting length of the /CE pin 24 is larger than a design value, lead formation defects may occur or quality defects, in which a package is suspended on a Pogo pin in a package test process, may occur.
Here, since the /CE pin 24 among the external leads of the upper package 20 is cut, a technique for applying a Chip Select signal to the upper package 20 is needed. To this end, a method of changing bonding wire (not shown) interconnections inside an upper package 20 and a method of changing external lead interconnections outside the upper package 20 may be considered.
In the former case of changing interconnections of bonding wires, one end of the bonding wire is bonded to a bonding pad (not shown) formed in a semiconductor chip, and the other end is connected to a No Select (hereinafter, referred to as NC) pin 21 of the upper package 20. The NC pin 21 of the upper package 20 is soldered with an NC pin 11 of the lower package 10, and a /CE signal of the upper package 20 is input through the NC pin 21 of the upper package 20. However, in this approach, the bonding wires inside the upper package 20 are entangled making an interconnection structure complicated. Also, bonding wire connecting structures of the upper package 20 and the lower package 10 do not coincide with each other so that work sequences and details have to be separated for a wire bonding process, which causes lowering of quality and productivity.
In the latter case of changing interconnections of external leads outside the upper package 20, a flexible circuit (not shown) or a connection member 30 for connecting the cut /CE pin 24 of the upper package 20 and the NC pin 11 of the lower package 10 are inserted between the upper and lower packages 10 and 20. However, the connection member 30 has to be aligned in a correct position. Thus, a process of stacking packages is complicated and if the connection member 30 is misaligned, a short may occur between external leads. The present invention addresses these and other disadvantages of the conventional art.